Integrated SiC Temperature Sensor Boosts Power Devices
In a recent article published in the journal Power Electronic Devices and Components, researchers from the United Kingdom present a novel design for a monolithically integrated silicon carbide-based temperature sensor within a 4H-SiC JFET (Junction Field-Effect Transistor). This integration aims to enhance the performance and reliability of power electronic devices by providing real-time temperature monitoring.
Background
The increasing demand for high-performance power electronic devices has driven significant advancements in semiconductor materials and technologies. Silicon carbide (SiC) has emerged as a leading candidate for high-voltage and high-temperature applications due to its superior thermal conductivity, wide bandgap, and high breakdown electric field compared to traditional silicon-based devices. As power electronic systems become more compact and efficient, the need for effective thermal management and real-time monitoring of junction temperatures has become paramount.
The Current Study
The device architecture consisted of a 4H-SiC JFET with an integrated lateral temperature sensor formed by a P+ gate implant. The sensor's resistance was designed to be temperature-dependent, relying on the ionization of dopants within the P+ region. The doping profile was engineered to achieve a high concentration of ionized acceptors, which increases with temperature, thereby affecting the sensor's resistance.
The fabrication process was outlined to include six distinct mask layers. Initially, a trench was etched to define the device structure. Subsequently, the P+ gate region, the temperature sensor, and a floating guard ring (FGR) were formed through simultaneous ion implantation. This approach minimized additional processing steps and allowed for efficient integration of the sensor into the existing JFET fabrication flow.
The simulations were conducted using Synopsys Technology Computer-Aided Design (TCAD), which facilitated both drift-diffusion and electrothermal modeling. The drift-diffusion simulations were essential for understanding the charge carrier dynamics and the temperature response of the sensor. The electrothermal simulations incorporated Fourier’s law of heat conduction to analyze the thermal behavior of the device under steady-state and transient conditions.
Key parameters such as hole mobility and doping concentration were incorporated into the models. The optimization process focused on several critical aspects, including the spacing between the sensor junction and the gate junction, as well as the doping concentration within the P+ region.
On comparing the simulation results with experimental data obtained from similar devices, the resistance values were found to align closely, with discrepancies attributed to contact resistance and variations in the doping profile. The study also included a detailed analysis of the impact of contact resistance on the overall sensor performance, confirming that it contributed minimally (≤1%) to the total resistance.
Results and Discussion
The integrated temperature sensor demonstrated a highly linear response over the temperature range of 25 °C to 150 °C, with a correlation coefficient (R²) of 0.996. This linearity indicates that the sensor can reliably track temperature changes, making it suitable for real-time monitoring applications in power electronics. The temperature sensitivity of the sensor was attributed to the increase in the number of ionized dopants in the P+ region as temperature rises, which directly influences the sensor's resistance.
The drift-diffusion simulations effectively captured the relationship between temperature and sensor resistance, confirming that the sensor's design allows for accurate temperature readings. The incorporation of incomplete ionization effects in the simulations was crucial, as it provided a more realistic representation of the sensor's behavior under varying thermal conditions.
The study found that the breakdown voltage (BV) of the JFET with the integrated sensor was 1334 V, which is a critical parameter for high-voltage applications. The optimization of the spacing (S) between the sensor junction and the gate junction was essential in achieving this high breakdown voltage. An optimal spacing of 0.95 μm was determined to balance the need for high BV while minimizing the variations in sensor current (ΔI_sens).
The analysis of sensor current variations revealed that ΔI_sens was influenced by the proximity of the sensor to the gate junction. The study reported a ΔI_sens of 3.34% at a drain voltage (V_d) of 1000 V, which is relatively low and indicates minimal cross-talk between the sensor and the gate junction. This low level of cross-talk is advantageous, as it ensures that the sensor can operate effectively without significantly affecting the performance of the JFET.
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